A TMR element is used in magnetic devices such as a Magnetic Random Access Memory (MRAM) structure and a magnetic read head. In FIG. 1, a TMR element 6 is shown wherein a stack of layers has a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. In an MRAM structure, the TMR element is commonly referred to as a magnetic tunnel junction (MTJ) and is formed between a bottom electrode 5 or bottom conductor and a top electrode 14 also known as a top conductor. The bottom conductor 5 typically has a seed layer/Cu/capping layer configuration and is used to connect the TMR element 6 to an underlying transistor (not shown). In a magnetic read head, the TMR element 6 is formed between a bottom shield and a top shield (not shown). The bottom (seed) layer 7 in the TMR element 6 is generally comprised of one or more seed layers that promote a smooth and dense crystal growth in overlying layers. Above the seed layer 7 is an anti-ferromagnetic (AFM) pinning layer 8 and a first ferromagnetic layer that is a “pinned” layer 9 on the AFM layer. The thin tunnel barrier layer 10 above the pinned layer 9 is generally comprised of a dielectric material such as AlOx that may be formed by first depositing an Al layer and then performing an in-situ oxidation. The tunnel barrier layer 10 must be extremely uniform over the wafer since small AlOx thickness variations result in large variations in resistance. A more uniform tunnel barrier is required for advanced TMR designs which means the underlying layers should have improved thickness uniformity. A ferromagnetic “free” layer 11 is formed on the tunnel barrier layer 10 and is typically less than 50 Angstroms thick to obtain low switching fields in the patterned bits. At the top of the TMR element is a cap layer 12.
The MTJ stack in FIG. 1 has a so-called bottom spin valve configuration. Alternatively, an MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, AFM layer, and a cap layer.
The pinned layer 9 has a magnetic moment that is fixed in the y direction by exchange coupling with the adjacent AFM layer 8 that is also magnetized in the y direction. The free layer 11 has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer 10 is so thin that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may switch in response to external magnetic fields generated by passing a current through the bottom conductor 5 and top conductor 14. It is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current 15 is passed from the top conductor 14 to the bottom conductor 5 (or top shield to bottom shield in a read head) in a direction perpendicular to the TMR layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
Referring to FIG. 2, the TMR (MTJ) element 6 is shown interposed between the bottom conductor 5 and a top conductor 14 in a MRAM structure 20. The substrate I is comprised of a transistor (not shown) that is typically connected to the bottom conductor by a stud 4. A digit line 3 (word line in a 1T1MTJ) is formed below the MTJ element 6 and within a first insulation layer 2 that is usually a composite layer consisting of a stack of two or more dielectric layers which are not shown in order to simplify the drawing. The MTJ element 6 contacts the top conductor 14 (bit line) through the capping layer 12 and is formed in a second insulation layer 13 that is disposed on the bottom conductor 5. From a top-down perspective (not shown), a plurality of MTJ elements is formed in an array between multiple rows of bottom conductors (word lines) and multiple columns of top conductors (bit lines). Each MRAM cell has its own bottom conductor.
Switching of the free layer magnetization in the MTJ bit is accomplished by applying currents in orthogonal directions. For instance, the MTJ element may be elliptical in shape from a top-down view with a long axis running parallel to the underlying digit or word line 3. Currents i1 running transversely in the bit line 14 and bottom conductor 5 are orthogonal to the current i2 in the digit line (MTJ) or word line 3 (1T1MTJ). Thus, the current i1 provides the field parallel to the easy axis of the bit while the current i2 provides the perpendicular (hard axis) component of the field. The intersection of the conductive lines generates a peak field that is engineered to be just over the switching threshold of the MTJ.
In a read operation, the information stored in an MRAM cell is read by sensing the magnetic state (resistance level) of the MTJ element through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM cell by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ element. In cross-point MRAM architecture, the top conductor or the bottom conductor participates in both read and write operations.
In addition to MRAM applications, a TMR element with a thinner tunnel barrier layer and a very low resistance×area (RA) value may be employed as a tunneling magnetoresistive (TMR) sensor between a bottom shield and top shield in a magnetic read head. A TMR sensor typically has a cross-sectional area of about 0.1 micron×0.1 micron at the air bearing surface (ABS) plane of the read head.
A high performance TMR element is characterized by a high TMR ratio which is dR/R where R is the minimum resistance of the TMR element and dR is the change in resistance observed by changing the magnetic state of the free layer. A higher dR/R improves the readout speed in an MRAM array. In order to achieve good tunnel barrier properties such as a specific junction resistance×area (RA) value and a high breakdown voltage (Vb), it is necessary to have a uniform tunnel barrier layer that is promoted by a smooth and flat underlying layers. For advanced TMR read head technology applications, a dR/R value above 20% and a RA value that is preferably below 10 ohm/μm2 are needed.
The performance of an MTJ element is enhanced according to U.S. Pat. No. 6,831,312 by incorporating an amorphous alloy such as CoFeB as the pinned layer and free layer in an MTJ stack. Boron is included in the alloy to control the recrystallization temperature and polarization of the resulting MTJ device.
In U.S. Pat. No. 6,479,096, a Pb surfactant layer is included in the deposition of a non-magnetic Cu spacer layer and promotes a face centered cubic Cu layer that is grown layer by layer to form a smooth surface. As a result, there is an improved interface between the Cu and adjacent layers that enhances sensor performance and reliability.
An oxide layer is formed as a magnetic domain control layer adjacent to a magneto-resistive sensor in U.S. Pat. No. 6,870,718. There may also be an oxide underlayer material between the magnetic domain control layer and sensor to prevent shunting from the magnetoresistive sensor to the magnetic domain control layer.
In U.S. Pat. No. 6,631,055, a flux guided MTJ is described wherein a pinned layer is comprised of an active and inactive region. The inactive region may be oxidized to reduce its electrical conductivity and lower the magnetic moment to near zero.
A CoFeB layer interposed between Cu layers in a CPP GMR spin valve is oxidized to provide an insulating barrier between the Cu layers in U.S. Patent Application 2003/0128481. The insulating barrier is a metal oxide with an undefined thickness.